The present invention relates to a semiconductor integrated circuit using bipolar transistors and, more particularly, a current source circuit which is improved in respect of the variation in the input/output current ratio due to the dispersions of elements and the change in ambient temperature.
FIG. 1 shows the constitutional arrangement of a conventional synchronous detection circuit as an example of a semiconductor integrated circuit provided with a current source circuit.
In this synchronous detection circuit, an input signal VIN superimposed on a DC bias voltage VB is supplied to the base of an NPN transistor Q1. Further, two pairs of NPN transistors Q2, Q3 and Q4, Q5 arranged in such a manner that the emitters of the transistors in the respective pairs are connected to each other are controlled in synchronism with switch control signals SW1, SW2 supplied to the bases of the respective transistors, whereby, from the common collectors of the transistors Q3, Q5, a detection output signal OUT is derived.
In this case, used as a load to the transistors Q2, Q3, Q4 and Q5 is a current mirror circuit (current source circuit) 10 comprised of PNP transistors Q6, Q7, Q8 and Q9, an NPN transistor Q10, and resistors R1, R2 and R3.
In this current mirror circuit 10, the emitter of the transistor Q6 is connected to a voltage node 11 through the resistor R1. A positive DC bias voltage VA is supplied to the node 11. The collector of the transistor Q6 is connected to a current input terminal 12. Also connected to this current input terminal 12 are the respective collectors of the transistor Q2, Q4. The emitter of the transistor Q7 is connected to the voltage node 11 through the resistor R2. The base of the transistor Q7 is connected commonly to the base of the transistor Q6, and the collector thereof is connected to a current output terminal 13. Also connected to this current output terminal 13 are the respective collectors of the transistors Q3, Q5. The emitter of the transistor Q9 is connected to the voltage node 11 through the resistor R3. The base and collector of the transistor Q9 are connected to the common bases of the transistors Q6 and Q7. The transistor Q9 and the resistor R3 are provided for preventing the current mirror circuit 10 from oscillating.
The collector of the transistor Q10 is connected to the common base of the transistors Q6 and Q7. The emitter of the transistor Q10 is connected to the emitter of the transistor Q8. The base of the transistor Q8 is connected to the collector of the transistor Q6, while the collector of the transistor Q8 is connected to a voltage node 14 which is supplied with the earth voltage.
Further, the circuit consisting of NPN transistors Q11, Q12, Q13 and Q14, resistors R4 and R5, and constant-current sources I1, I2, I3 and I4 feeds the common emitter of the transistors Q2, Q3 and the common emitter of the transistors Q4, Q5 with a current corresponding to the input signal VIN or a current corresponding to the constant voltage generated by a constant-voltage generation circuit to be described later, the circuit being constituted as follows:
That is, the bases of the transistors Q11, Q12 are connected to the emitter of the transistor Q1. The collector of the transistor Q11 is connected to a node N1 which is supplied with the constant voltage, while the emitter thereof is connected through the constant-current source 11 to the voltage node 14 placed at the earth voltage. The collector of the transistor Q12 is connected to the common emitter of the transistors Q2, Q3, while the emitter thereof is connected to the voltage node 14 through the constant-current source I2. The bases of the transistors Q13, Q14 are connected to the node N1. The collector of the transistor Q13 is connected to the common emitter of the transistors Q4, Q5, while the emitter thereof is connected to the voltage node 14 through the constant-current source I3. The collector of the transistor Q14 is connected to the emitter of the transistor Q1, while the emitter thereof is connected to the voltage node 14 through the constant-current source I4.
Further, between the emitters of the transistors Q12, Q13, the resistor R4 is connected, while between the emitters of the transistors Q11, Q14, the resistor R5 is connected.
The circuit consisting of PNP transistors Q15, Q16, Q17, NPN transistors Q18, Q19, and a resistor R6 constitutes a constant-voltage generation circuit. That is, the emitter of the transistor Q15 is connected to the voltage node 11 through the resistor R6. The emitter of the transistor Q16 is connected to the voltage node 11, while the base thereof is connected to the base of the transistor Q15. Further, the base and collector of the transistor Q16 are short-circuited to each other. The collector and base of the transistor Q18 are connected to the collector of the transistor Q15. Further, a common connection node N2 between the collector and base of the transistor Q18 is connected to the base of the transistor Q10. The emitter of the transistor Q17 is connected to the emitter of the transistor Q18.
The collector of the transistor Q19 is connected to the collector of the transistor Q16. Further, the bases of the transistors Q17, Q19 are commonly connected to each other, and, to these commonly connected bases, a DC bias voltage VB is supplied. The collector of the transistor Q17 is connected to the voltage node 14, and the emitter of the transistor Q19 is connected to the node N1.
By the way, in a current mirror circuit in general, there is provided means for correcting the error in the input/output current ratio which is caused by the base currents of transistors etc.; and, in the case of the current mirror circuit 10 shown in FIG. 1, the transistors Q8 and Q10 are provided for correcting the error in the input/output current ratio due to the base current of the transistors Q6, Q7 and the base-collector current of the transistor Q9, and further, a current of a value corresponding to the currents which cause the error is made to flow to the earth voltage node through the transistor Q8.
However, the base current itself of the correcting transistor Q8 joins to the collector current of the transistor Q6; and thus, the base current causes an error in the input/output current ratio of the current mirror circuit.
Due to this, in the circuit shown in FIG. 1, a correction circuit 20 is further provided to correct the error due to the base current of the transistor Q8.
This correction circuit 20 is comprised of PNP transistors Q20, Q21, and a resistor R7. That is, the emitter of the transistor Q20 is connected to the voltage node 11 through the resistor R7, while the base thereof is connected to the common base of the transistors Q6, Q7 in the current mirror circuit 10. The emitter of the transistor Q21 is connected to the collector of the transistor Q20, the base thereof is connected to the collector of the transistor Q7 in the current mirror circuit 10, and the collector thereof is connected to the voltage node 14.
In the correction circuit 20, the transistor Q20 constitutes a current mirror together with the transistor Q6 in the current mirror circuit 10. Further, by setting the value of the resistor R7 so that the base currents of the transistors Q8 and Q21 may become equal to each other, the sum of the collector current of the transistor Q6 and the base current of the transistor Q8 and the sum of the collector current of the transistor Q7 and the base current of the transistor Q21 are equalized to each other. By so doing, the error in the input/output current ratio caused by the base current of the transistor Q8 is corrected.
By the way, in the conventional circuit shown in FIG. 1, the value of the base current of the transistor Q8 becomes 1/hfe (wherein hfe stands for the current amplification factor) times as large as the total sum of the base current of the transistor Q6, the base current of the transistor Q7, the base current and collector current of the transistor Q9, and the base current of the transistor Q20. The correction for the base current of the transistor Q8 is made by only the base current (which is 1/hfe times as large as the collector current of the transistor Q20) of the transistor Q21.
Due to this, even if the value of the base current of the transistor Q21 is set or adjusted under a certain condition, an unbalance is caused between the base currents of the transistors Q8 and Q21 in some cases due to the dispersions of the elements and the variation in ambient temperature. As a result, there arises the problem that the values of the currents which flow to the node 13 at which the detection output signal OUT is derived and to the node N3 which is paired with the node 13 and is the common collector node of the transistors Q2, Q4 are varied due to the dispersions of the elements and the variation in the ambient temperature, as a result of which the input/output current ratio comes to vary.
Further, so far, the potential at the node N3 paired with the node at which the detection output signal OUT is derived is determined by the VB+VBE (Q17)+VBE (Q18)-VBE (Q10)-VBE (Q8), wherein VBE (Qi) (i=1, 2 . . . ) stands for the base-emitter voltages of the respective transistors. However, the potential at the node at which the detection output signal OUT is obtained is not determined unconditionally, becoming indeterminate. Due to this, there has also been caused the problem that the values of the emitter-collector voltages VCE of the transistors Q6 and Q7 become different from each other; and, by the influence of the early effect, the collector currents of the transistors Q6 and Q7 become unbalanced.